tl;dr: IBM unveiled a 0.7 nm ("7 angstrom") chip using a new "nanostack" 3D architecture that vertically stacks and staggers nanosheet transistors, fitting ~100 billion transistors on a fingernail-sized die. The company claims up to 50% better performance or 70% better energy efficiency over its 2 nm node, plus 40% SRAM scaling, with production possibly within five years. Work continues at IBM's Albany facility alongside ASML High-NA EUV and partners like Lam, TEL, and SCREEN.